As computers advance, integration of platforms and their components become a larger and more complex task. As devices within computers continue to evolve, the speed at which the devices internally run increases. To this end, interconnects between devices become a limiting performance factor, if the speed at which the interconnects transmit data is not increased. Previously, interconnects at much slower speeds were much more concerned with the digital design of the output buffer, as compared to the integrity of signals transmitted.
However, as speeds of transmitted signals on interconnects have progressed from MHz to GHz, the need for better signal integrity has become essential. As the frequency of transmitted signals continue to increase timing and signal integrity is even more important in ensuring that valid and correct data is transmitted. Unfortunately, a design of a single buffer and a single trace of an interconnect is not enough to ensure good signal integrity on a bus. Since traces are present in the same dielectric and are often made of conductive material, cross-coupling with surrounding traces may significantly affect the performance and integrity of signals on a victim trace.
A simple way of viewing this interdependency is illustrated in FIG. 1. Although a greater number of traces may be present in forming an interconnect, only three traces are depicted in FIG. 1, which include, aggressor line 105, victim line 110, and aggressor line 115. When a signal is transmitting on aggressor lines 105 and 115, cross-coupling, also referred to as crosstalk, occurs between the aggressor lines and victim line 110. One of the potentially worst case crosstalk scenarios for timing windows is shown in FIG. 1, where aggressor lines 105 and 115 are transitioning in the opposite direction of victim line 110. In this case, some ringing, or other adverse signal integrity effect, may be induced by aggressor lines 105 and 115 causing crosstalk 120.
Since designers often take worst-case scenarios into account when designing interconnects, the opposing transitions illustrated in FIG. 1 often limits bus performance.